SYSTEMS & HARDWARE ENGINEER

Hi, my name is

Chayan Deb.

Hardware Logic. Software Brains.

Electronics Engineer & Part-Time Developer Building Cool Stuff.

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FPGA & [0/1] Design • CUDA & C/C++ • Edge-AI & ML • Kernel & Systems
01 // BACKGROUND & SKILLS

About Me

I have completed my B.Tech in Electronics and Electrical Engineering from IIT Palakkad, Kerala.

Currently interested in the fields of IoT, ML & CV, Microprocessors, Robotics, Communication Engineering & a little bit of Cybersecurity.

Technical Arsenal

Hardware & Core

7 DOMAINS
  • Systems-Level Programming
  • GPU Acceleration (CUDA/ROCm/HIP)
  • Digital System Design (Verilog HDL)
  • Arduino (Firmware/Assembly/C)
  • Python & MATLAB Programming
  • Semiconductor Device Fabrication
  • LabView Automation

Software & AI

7 DOMAINS
  • x86 & ARM Assembly, C/C++, Rust
  • HPC Cluster Operation
  • AI & Machine Learning (PyTorch)
  • Computer Vision (OpenCV/PIL)
  • Full-Stack Web (MSRN)
  • 3D Web (ThreeJs/Blender)
  • App Dev (Tauri/Flutter)
02 // MILESTONES & EDUCATION

Timeline

B.Tech Electronics & Electrical Engineering

IIT Palakkad | July 2018 – April 2022

  • Semifinals Qualifier in Swadeshi Microprocessor Challange (Top 100 teams, MeitY - Govt. of India, 2021).
  • Final Round Qualifier in HCL Hack IITK Cybersecurity Hackathon (Top 109 teams, IIT Kanpur, 2020).
  • Stage-I Qualifier in E-Yantra Robotics Competition (IIT Bombay, 2019).
  • Qualified in Texas Instruments Design Challenge (IIM Bangalore, 2018).

Higher Secondary (+2 Stage)

Netaji Subhas Vidyaniketan | April 2016 – April 2018

  • Secured 5th position in State Board (TBSE) H.S. (+2) Examination.
  • 1st Place Holder in State level Chemistry Olympiad (2018).
  • 6th Place Holder in State level Chemistry Olympiad (2017).

Secondary (10th Stage)

Netaji Subhas Vidyaniketan | Graduated April 2016

  • 1st Place Holder in State level Chemistry Olympiad (2016).
  • Qualified NTSE Stage-I (2016).
03 // PROFESSIONAL EXPERIENCE

Where I've Worked

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Xschem EDA Software

Open-Source Contributor

Xschem (EDA Software) | Jan 2025 – Mar 2025

EDAANSI-CTCLCMake
  • Delivered TCL and C-based structural upgrades for Xschem, a robust & open-source alternative to Cadence Virtuoso.
  • Authored and merged complex schematic grid-snapping logic and orthogonal wire placement algorithms.
  • Directly improved circuit design workflows and graphical wire routing for end-users.
Systems & Software Consultant

Systems & Software Developer

Independent Consultant | Sept 2022 – Mar 2025

C/C++OpenCVCUDAOpenMP
  • Delivered 25+ custom systems-level software projects.
  • Projects involved Parallel Programming, CV & Image Processing, and GPU-Accelerated 3D Rendering Logic for independent global clients across the USA, UK, China, and Austria.
  • Retained an overall 5-star client satisfaction level across all delivered projects and platforms.
IIT Palakkad Embedded Systems Group

Co-Founder & Hardware Lead

IIT Palakkad Embedded Systems Group | Aug 2021 – Feb 2022

OBD-IIEdge-MLFPGA
  • Designed a Driving Behavior Evaluation System utilizing the vehicle's OBD-II port for real-time data collection.
  • Combined with ML-based data analysis algorithms deployed on low-compute edge devices.
  • Secured INR 1,00,000 seed funding from MeitY (Under Govt. of India) to build an operational MVP of a novel hardware product.
04 // FEATURED BUILDS

My Projects

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Local LLM Inference Engine

Local LLM Inference Engine

llama.cpp, CMake, C++ | Feb 2026 – Mar 2026

llama.cppC++CMakeRAG
  • Developed a localized command-line shell program to run quantized Gemma-4 LLM models (E2B, E4B, E12B with 8bit quantization) locally.
  • Implemented a basic RAG system using MySQL and plaintext source files.
  • Built dynamic token resolution natively in C++ for fast local inference.
Magnetic Property AI Prediction

Magnetic Property AI Prediction

Computational Physics, PyTorch | Jan 2026 – Apr 2026

PyTorchDFTMLTransformer
  • Reproduced DFT-calculated prediction of known Heusler Alloy molecular stability & magnetic properties with >85% accuracy.
  • Benchmarked machine learning paradigms (Random Forest, SVMs, Transformers) against elemental data.
  • Isolated optimal predictive feature combinations for magnetic moments and Curie temperatures.
GPU Rainbow Table Builder

GPU Rainbow Table Builder

Parallel Programming, SHA-3, CUDA, C | Nov 2024 – Dec 2024

CUDACSHA-3Cryptography
  • Designed and implemented a GPU-Accelerated Rainbow-Table generator using NVIDIA CUDA framework.
  • Implemented custom parallel 256-bit SHA-3 hashing algorithm processing 16-bit UUID values.
  • Generated both compressed and uncompressed rainbow table files for high-throughput cryptographic analysis.
CPU Task Scheduler Simulation

CPU Task Scheduler Simulation

Operating Systems Simulation, C | Nov 2024 – Dec 2024

COS ArchitecturePthreads
  • Designed CPU task schedulers simulating core OS allocation algorithms including FIFO, SJF, and Priority Scheduling.
  • Modeled context switching, dynamic process control block (PCB) memory management, and hardware interrupt handling.
  • Optimized task turnaround and baseline wait times across virtual CPU cores.
Math Compute Server

Math Compute Server

Pthreads, Distributed C | July 2024

CPthreadsHPC
  • Developed a daemonizable, multi-threaded server architecture in pure C to offload compute-heavy parallelizable mathematical workloads.
  • Implemented and optimized parallelized K-Means clustering algorithm.
  • Optimized Gauss-Jordan elimination for matrix inversions, accelerating linear algebra operations across distributed client instances.
RISC-V Shakti Microprocessor

Swadeshi Microprocessor

RISC-V Shakti C-Class VAJRA | Aug 2020 – Aug 2021

Artix-7RISC-VFPGA
  • Qualified for the semifinals (Top 100) under Ministry of Electronics (MeitY).
  • Developed PoC using the 64-bit C-Class VAJRA Microprocessor.
  • Designed under IIT Palakkad Embedded Systems Group.
Petrichor Backend

Petrichor Backend

Web Backend for IIT Palakkad Fest | Aug 2020 – Jan 2021

NodeJSMongoDBExpress
  • Designed the backend and deployment using NodeJS and MongoDB.
  • Implemented backend structure for the CA-Portal of the server.
  • Handled Email-Verification of users on the server.
High-Frequency Waveguide Design

High-Frequency Waveguide Design

Ansys HFSS Electromagnetic Simulator | Jun 2020 – Jul 2020

Ansys HFSSElectromagneticsRF
  • Engineered E-Plane and H-Plane Tees utilizing standard rectangular waveguides (WR-90) for X-band RF signal propagation.
  • Conducted extensive electromagnetic field simulations utilizing Ansys HFSS software.
  • Validated structural resonance, impedance matching, and Poynting vector flux parameters.
ISRO Satellite Segmentation

ISRO Satellite Image Mapper

Machine Learning based Mapper for SIH-2020 | Mar 2020 – Aug 2020

MLU-NetTensorFlowPython
  • Built a U-Net based FCNN architecture for Semantic Segmentation on multi-channel (IR, Red, Green) geospatial data.
  • Manually labeled ground truth dataset for unique 5m-resolution images with >90% inference accuracy.
  • Qualified for the SIH-2020 Grand Finals in Software Problems.
Tinder Automator

Tinder Automator

Tinder Matchmaker & Bot using Python | Mar 2020 – May 2020

SeleniumTensorflowPython
  • Built an automated Tinder bot using Selenium Webdriver.
  • Trained an ML model to classify profiles and automate swiping.
  • Collected profile images locally to build a computer database.
FaceNet FaceID

FaceNet FaceID

Facial Recognition System using Keras | Feb 2020 – Apr 2020

ConvNetsKerasTransfer Learning
  • Utilized a FaceNet model to derive a unique 128 cell feature vector.
  • Measured Euclidean distance between faces to predict similarity.
  • Gained deep understanding of Transfer Learning and ConvNets.
Automated System Payload Injector

Automated System Payload Injector

Embedded-C, Arduino | Feb 2020

Embedded-CFirmwareHID Protocol
  • Developed custom firmware for an Arduino microcontroller to emulate a USB keyboard using standard HID protocol.
  • Engineered automated keystroke injection payloads for automated system deployment and validation.
  • Tested on hardware microcontrollers with zero latency.
8-bit Microcomputer & Assembler

8-bit Microcomputer & Assembler

Von Neumann Architecture using Verilog HDL | Oct 2019 – Apr 2020

Verilog HDLFPGAAssembly
  • Designed & systematically simulated a fully operational 8-bit microcomputer in Verilog HDL (62 stars, 16 forks on GitHub).
  • Created a custom cross-assembler via Python to translate human-readable assembly instructions directly into binary machine code.
  • Validated digital logic operations using open-source iverilog & GTKWave.
05 // DISPATCH & INQUIRIES

Get In Touch

I'm currently looking for new opportunities. Whether you have a question, a project idea, or just want to say hi, my inbox is open!